The present invention relates to digital logic circuits and, more particularly, to multi-bit flip-flops.
FIG. 1 is a schematic circuit diagram of a conventional one-bit, rising-edge-triggered, master-slave D flip-flop (also known as a static D flip-flop or SDFF) 10. The SDFF 10 comprises a master latch 11 and a slave latch 15. During a first phase of a system clock signal CK, the master latch 11 receives and latches a one-bit FF input signal D and, during the next phase of the system clock signal CK, the slave latch 15 receives the one-bit output signal m from the master latch and presents a one-bit FF output signal Q, while the master latch 11 receives and latches the next value of the one-bit FF input signal D.
In particular, a clock source 103 receives the system clock signal CK and includes a pair of inverters 104 and 106 connected in series to generate opposite-phase and in-phase clock signals cn and c, which it supplies to the flip-flop 10.
The master latch 11 comprises first and second clocked inverter stages 12 and 14 and a first (unclocked) inverter INV1. The first stage 12 has a p-type complementary metal-oxide semiconductor (PMOS) clock switch SP1, a PMOS MP1, an n-type CMOS (NMOS) data device MN1, and NMOS clock switch SN1, all connected in series. The second stage 14 has analogous data device MP2 and MN2 and clock switches SP2 and SN2, all connected in series.
Similarly, the slave latch 15 includes third and fourth clocked inverter stages 16 and 18, having analogously configured data devices MP3, MN3, MP4, and MN4 and clock switches SP3, SN3, SP4, and SN4, and a second (unclocked) inverter INV2.
When the clock signal c is low and the clock signal cn is high, the first stage 12 is on, and the data output pm of the first stage 12 will be the opposite of its data input D. Similarly, the fourth stage 18 is on, and the data output ss of the fourth stage 18 will be the opposite of its data input Q. When the clock signal c is high and the clock signal cn is low, the first and fourth stages 12 and 18 will be off.
On the other hand, when the clock signal c is high and the clock signal cn is low, the second stage 14 is on, and the data output pm of the second stage 14 will be the opposite of its data input m. Similarly, the third stage 16 is on, and the data output ss of the third stage will be the opposite of its data input m. When the clock signal c is low and the clock signal cn is high, the second and third stages 14 and 16 will be off.
The data output signals of the first and second stages 12 and 14 appear at the node pm. The data input signal of the second and third stages 14 and 16 is provided by the data output signal of the first inverter INV1 at the node m, which is the output of the master latch 11 and the input of the slave latch 15. The data output signals of the third and fourth stages 16 and 18 appear at the node ss. The data input signal of the fourth stage 18 is provided by the data output signal of the second inverter INV2 at the node Q, which is at the output of the slave latch 15 and the output of the D flip-flop 10.
Since a large number of flip-flops may be used in a typical integrated circuit (IC), the cumulative power consumption of all of the flip-flops can be significant. Various techniques have been used to reduce the power consumption of flip-flops.
Clock signal switching is inherently more frequent than data signal switching and therefore typically accounts for a larger proportion of the power consumption than data signal switching. One known technique for reducing power consumption involves gating (switching OFF) the clock signals when the flip-flop output is equal to its input. Another known technique uses dynamic logic, instead of static logic, to reduce the number of components. However, most known techniques used to reduce power consumption have the disadvantages of increasing circuit area and/or leading to performance penalties such as increased set-up or hold times, clock glitches, and the risk of unstable operation.